University Wednesday , 10 May 2000 Trace Cache

Due to unfortunate circumstances this lecture was not scribed, following are several points that I remember were brought up. If anyone has something to add please tell me. In this session we discussed three papers: Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism-describes several enhancements to the original University of Michigan view of the trace cache. Path-Based Next Trace Prediction-introduces a different way of predicting and indexing traces for the University of Wisconsin trace cache. This patent describes an instruction cache variant designed specifically for superscalar processors. It improves instruction fetch throughput while allowing a single fetched line to cross basic-block boundaries, and removing the alignment constraints of conventional instruction caches. This organization is also amenable to solving some of the more specific fetch issues of CISC processors, i.e. variable length instructions. The trace cache is organized around traces which are single-entry multiple-exit sequences of dynamically executed instructions. This is in contrast to conventional instruction caches which use sequential memory addresses as their basic line of instructions. Branch prediction information is tightly integrated with the instructions to allow fetches that also cross basic-block boundaries. A trace can contain several basic blocks that are implicitly predicted to follow one another. By fetching an entire trace many of the shortcomings of conventional instruction caches are circumvented. In instruction caches lines are aligned on address boundaries which have little to do with the actual fetch patterns, also frequent branches cause only a small part of each line fetched to be usable, as seen in the collapsing-buffer paper of